The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having an improved margin of a pulse width and enabling timing of a pin strobe signal that determines a timing of loading data on a pipelatch.
As a synchronous dynamic random access memory (SDRAM) has been continuously developed from single data rate (SDR) to double data rate (DDR), DDR2, DDR3, etc, a prefetch scheme is used in DDR/DDR2/DDR3 SDRAMs.
The prefetch scheme is used to overcome a limitation caused by a difficulty in increasing an operating speed of a core region of a semiconductor memory device. In the prefetch scheme or architecture, data is processed in parallel at the core region where it is difficult to increase an operating speed, and the data is rapidly input/output in series at an input/output (I/O) region.
For example, a DDR2 SDRAM employs a 4-bit prefetch scheme in which 4-bit data are read from memory cells in parallel according to a read command, and the read 4-bit data are output in series through the identical data pin (DQ pin) during two clock cycles.
As is well known, an apparatus that sequentially outputs data in series through the data pin is necessarily required to use the prefetch scheme. Such an apparatus is called a pipelatch. To determine a timing of loading the data on the pipelatch, a pin strobe signal or a pipelatch input signal is needed, which generally is represented as a symbol of PIN.
Data to be output during a read operation, and a pin strobe signal for determining the timing of loading the data on the pipelatch are transferred to the pipelatch from a bank. The data is transferred through a global input/output (GIO) line and experiences an RC delay. In this case, delay values of the data are not greatly changed in spite of process-voltage-temperature (PVT) variations because the RC delay has little effect on the PVT variation. However, the pin strobe signal is transferred to the pipelatch while passing through a variety of logic devices, and thus delay values of the pin strobe signal are greatly changed according to the PVT variations.
FIG. 1 is a block diagram illustrating a preliminary pin strobe signal generating unit of a conventional semiconductor memory device. The preliminary pin strobe signal generating unit may be provided around a bank of the semiconductor memory device.
The preliminary pin strobe signal generating unit includes a delay line 101, a NAND gate 103 and inverters 102 and 104. A preliminary pin strobe signal PRE_PIN is generated through a combination of a column address strobe (CAS) pulse signal CAS_PULSE and a write I/O sense amplifier signal WT_IOSA. The CAS pulse signal CAS_PULSE is an internal pulse signal generated by a column command, e.g., write/read command. The write I/O sense amplifier signal WT_IOSA has a logic high level in a write operation and a logic low level in a read operation.
When the write I/O sense amplifier signal WT_IOSA of a logic low level is input in a read operation and the CAS pulse signal CAS_PULSE of a logic high level is input, the NAND gate 103 receives two high-level signals to output a pulse signal that is activated to a logic low level. This pulse signal is inverted through the inverter 104 so that the preliminary pin strobe signal PRE_PIN, which is activated to a logic high level, is output. In short, the preliminary pin strobe signal PRE_PIN is activated around a band during the read operation.
An I/O sense amplifier strobe signal IOSTBP is a column-based sense amplifier strobe signal for reading data of a bank during the read operation, and determines a timing of loading data on global input/output (GIO) lines from the bank. The I/O sense amplifier strobe signal IOSTBP is obtained by modulating a pulse width and delay time of the preliminary pin strobe signal PRE_PIN, which is shown in the lower part of FIG. 1. The preliminary pin strobe signal PRE_PIN is fed to a pulse modulation circuit 109 via a delay line 105. The pulse width of the I/O sense amplifier strobe signal IOSTBP is determined according to a delay value of a delay line 106 in the pulse modulation circuit 109, which combines the signal delayed by the delay line 106 with a signal that bypasses the delay line 106 in NAND gate 17.
FIG. 2 is a block diagram illustrating a pin strobe signal generating unit. The pin strobe signal generating unit generates a pin strobe signals PIN using the preliminary pin strobe signal PRE_PIN of FIG. 1.
The pin strobe signal generating unit includes an inverter 201, a delay line 202, NAND gates 203 and 204, and a pulse width modulation circuit 205. The preliminary pin strobe signal PRE_PIN is delayed by the delay line 202 and has a pulse width modulated by the pulse width modulation circuit 205 so that the pin strobe signal PIN is output.
Two NAND gates 203 and 204, which are cross-coupled to form a latch, are used to prevent the pin strobe signal PIN from being generated while a reset signal RSTB is activated to a logic low level. Since the reset signal RESTB is deactivated to a logic high level while a memory device is operating, the NAND gate 203 acts as an inverter simply during the operation of the memory device.
In the pulse width modulation circuit 205, a NAND gate 208 performs a NAND operation on an output signal of the NAND gate 203 and a signal obtained by delaying and inverting the output signal of the NAND gate 203 through a delay line 206 and an inverter 207, and thereafter an inverter 209 inverts an output signal of the NAND gate 208, thereby outputting the pin strobe signal PIN with the pulse width modulated. The pin strobe signal PIN has a pulse width corresponding to a delay value of the delay line 206.
Although the pin strobe signal generating unit of FIG. 2 may be positioned anywhere on a transfer path of the preliminary pin strobe signal PRE_PIN from a bank to a pipelatch, it is positioned around the pipelatch in general.
FIG. 3 is a timing diagram illustrating an operation of the pin strobe signal generating unit of FIG. 2.
Referring to FIG. 3, a PRE_PINBD signal, which is generated by inverting and delaying the preliminary pin strobe signal PRE_PIN through the inverter 201 and the delay line 202, is activated to a logic low level. The PRE_PINBD signal is inverted by the NAND gate 203 and its pulse width is modulated by the pulse width modulation circuit 205, so that the pin strobe signal PIN is output finally. The pin strobe signal PIN has the same pulse width as the delay value of the delay line 206 in the pulse width modulation circuit 205.
FIGS. 4A to 4D are timing diagrams of the pin strobe signal and data transferred through GIO lines during a read operation.
In FIGS. 4A to 4D, a reference symbol ‘GIO’ denotes a timing of data transferred to a pipelatch disposed around a data pin (DQ pin) from a bank through the GIO line, and a reference symbol ‘PIN’ denotes a timing of the pin strobe signal PIN transferred to the pipelatch through logic devices or the like. While the pin strobe signal PIN is activated, the pipelatch is enabled so that valid data of the GIO line is loaded on the pipelatch. To properly load the valid data on the pipelatch, therefore, the pin strobe signal PIN with a sufficient pulse width should be activated within a period for the valid data.
FIG. 4A is a timing diagram illustrating the valid data and the pin strobe signal PIN in the front of the pipelatch (i.e., around the DQ pin) under FAST PVT condition. The FAST PVT condition is a fast operating condition in which a process (P) is performed for a circuit to have fast characteristics, a voltage (V) is high, and a temperature (T) is low. Since the operating speed of a circuit is fast under the FAST PVT condition, a delay time caused by a logic device of the circuit may be relatively small. At this time, a pulse width also decreases, that is, the delay value of the delay line 206 decreases. If the pulse width, i.e., a width of an activation period of the pin strobe signal PIN, becomes too narrow, the valid data may not be loaded on the pipelatch properly.
FIG. 4B is a timing diagram illustrating the valid data and the pin strobe signal PIN under SLOW PVT condition. The SLOW PVT condition is a slow operating condition in which a process (P) is performed for a circuit to have slow characteristics, a voltage (V) is low, and a temperature (T) is high. In FIG. 4B, a reference symbol ‘TGIO’ indicates a delay time of the GIO line (data) in the SLOW PVT condition compared to the FAST PVT condition, and a reference symbol ‘TLD’ indicates a delay time of the pin strobe signal PIN in the SLOW PVT condition compared to the FAST PVT condition. When comparing the two delay times TGIO and TLD, it can be appreciated that the delay time TGIO is relatively smaller than the delay time TLD. This is because the delay time TLD is resulted from a variation of a logic delay with a PVT variation but the delay time TGIO is resulted from a variation of an RC delay with the PVT variation.
FIG. 4C is a timing diagram illustrating the valid data and the pin strobe signal PIN having an increased pulse width under FAST PVT condition so as to overcome problems caused by the narrow pulse width of the pin strobe signal PIN in FIG. 4A. That is, the delay line 206 of FIG. 2 is designed to have a greater delay value in FIG. 4C than that of FIG. 4A. Therefore, the activation timing of the pin strobe signal PIN in FIG. 4C is the same as that of the pin strobe signal PIN in FIG. 4A but its activation period, i.e., pulse width, becomes larger. Accordingly, data can be stably loaded on the pipelatch under the condition of FIG. 4C.
FIG. 4D is a timing diagram illustrating the valid data and the pin strobe signal PIN having an increased pulse width under SLOW PVT condition. Under this condition, a delay time is increased so that an activation timing of the pin strobe signal PIN is delayed and a pulse width of the pin strobe signal PIN also increases. Hence, it can be observed that the activation period of the pin strobe signal PIN falls out of the period for the valid data. If the activation period of the pin strobe signal PIN falls out of the period for the valid data, invalid data subsequent to the valid data or no data may be loaded on the pipelatch.
In summary, if the pin strobe signal PIN is set to have a narrow pulse width, the valid data may not be loaded on the pipelatch properly under the FAST PVT condition of FIG. 4A. On the other hand, if the pin strobe signal PIN is set to have a large pulse width, the activation period of the pin strobe signal PIN falls out of the period for the valid data under the SLOW PVT condition of FIG. 4D so that invalid data subsequent to the valid data may be loaded on the pipelatch.
The period for the valid data may be increased. However, the increase of the period for the valid data is limited by TCCD in the GIO lines. The TCCD is a parameter indicating how fast column commands such as read and write commands are sequentially input. The DDR2 standard specifies TCCD=2*tCK, and the DDR3 standard specifies TCCD=4*tCK.
Therefore, one clock cycle (tCK) should be increased to broaden the period for the valid data. To increase the one clock cycle (tCK), however, the operating speed should be lowered.